A High Speed RNS FIR Digital Filter Architecture with Totally Self Checking Code Error Detection

Several Digital Signal Processing (DSP) structures based on Residue number systems (RNS) have been proposed in the technical literature. Most of them employ a look up table approach, that is highly space inefficient and slow. In this regard, we propose a memoryless high-speed error detecting FIR filter architecture using 1-out-of-n code for representing the residue numbers. With the use of 1-out-ofn code, error detection is achieved without any redundant moduli. The proposed design exhibits VLSI efficient layout, operand independent delay and low power consumption. We also propose a technique to achieve direct analog output from the system.